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19-2375; Rev 0; 4/02
Dual-Rate Fibre Channel Limiting Amplifiers
General Description
The MAX3274/MAX3276* dual-rate Fibre Channel limiting amplifiers are optimized for use in dual-rate 2.125Gbps/1.0625Gbps Fibre Channel optical receiver systems. An on-chip selectable fourth-order Bessel Thompson filter offers 15dB (typ) of attenuation at 2GHz to suppress the relaxation oscillation (RO) found in legacy transmitters. The amplifiers accept a wide range of input voltages and provide constant-level output voltages with controlled edge speeds. Receivers using the MAX3275/MAX3277 transimpedance amplifiers (TIA) and the MAX3274/MAX3276 dual-rate limiting amplifiers can meet the Fibre Channel receiver sensitivity optical modulation amplitude (OMA) specification of 49mWP-P at 2.125Gbps and 31mWP-P at 1.0625Gbps. Additional features include a programmable threshold loss-ofsignal (LOS) detector, output squelch, and bandwidth select. The MAX3274/MAX3276 feature current-mode logic (CML) data outputs. The MAX3274/MAX3276 are available in 16-pin QFN packages, making them ideal for GBIC and small form-factor receiver modules. *Future product o On-Chip Selectable 4th-Order Filter o Relaxation Oscillation Suppression of Legacy, CD Laser-Based Transmitters o Available in 100 and 150 Output Terminations o Programmable Loss-of-Signal (LOS) Threshold o Output Squelch Control o Power-On Reset Minimizes Inrush Current o 4mm 4mm 16-Pin QFN Packages
Features
o Dual-Rate 1.0625Gbps/2.125Gbps Operation
MAX3274/MAX3276
Ordering Information
PART MAX3274UGE MAX3276UGE* TEMP RANGE 0C to +85C 0C to +85C DIFF OUTPUT PINTERMINATION PACKAGE 100 150 16 QFN 16 QFN
Applications
Fibre Channel GBIC Optical Modules Dual-Rate Fibre Channel SFF/SFP Optical Modules
*Future product--contact factory for availability
Typical Operating Circuit
OPTICAL MODULE RECEIVER SECTION +3.3V +3.3V HOST SERVER OR SWITCH HOST VCC
VCC
LOS LOS
4.7k TO 10k RX LOS DESERIALIZER 0.1F
0.1F
IN+
OUT+ 100 OR 150
TIA
0.1F INOUT-
0.1F
MAX3275
MAX3274 MAX3276*
TH SQUELCH GND BWSEL RATE SELECT
*FUTURE PRODUCT
Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual-Rate Fibre Channel Limiting Amplifiers MAX3274/MAX3276
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ............................................-0.5V to +6.0V Continuous CML Output Current (OUT+, OUT-) ...............................................-25mA to +25mA CML Input Voltage (IN+, IN-) .....................-0.5V to (VCC + 0.5V) Differential Input Voltage (IN+, IN-).....................................2VP-P TTL Input Voltage (BWSEL, SQUELCH, TEST) ....................-0.5V to (VCC + 0.5V) Voltage at TH ................................................-0.5V to VCC + 0.5V Current into TH...................................................................5.0mA Open Collector (LOS, LOS)...................................-0.5V to +5.5V Operating Ambient Temperature Range .............-40C to +85C Storage Ambient Temperature Range...............-55C to +100C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.)
PARAMETER Supply Current Data Rate BWSEL = 0 BWSEL = 1 -3dB, BWSEL = 0 (Note 1) Small-Signal Bandwidth BWSEL Response Time Input Range Deterministic Jitter VIN -15dB, BWSEL = 0 (Note 1) -3dB, BWSEL = 1 (Note 1) (Note 2) (Notes 2, 3) BWSEL = 0, 10mV input 20mV (Notes 2, 4) BWSEL = 0, 20mV < input 1200mV (Notes 2, 4) BWSEL = 1, 10mV input 1200mV (Notes 2, 4) Random Jitter Total Jitter LOS, LOS Transition Time LOS, LOS Response Time LOS, LOS Hysteresis LOS Assert (VLOS) Range LOS Assert (VLOS) Error Squelch Input Current Single-Ended Input Resistance Data Input VSWR Differential Output Resistance CML Output Voltage Data Output Levels ROUT VOUT RIN IN+, IN- to VCC f < 2GHz (Note 2) OUT+ to OUT- (MAX3274) OUT+ to OUT- (MAX3276) SQUELCH = 0 (Note 4) SQUELCH = 1, VIN < VTH (Note 4) SQUELCH = 1, VIN < VTH (Note 4) VCC - 0.1 80 120 900 100 150 1200 40 50 BWSEL = 0 (Notes 2, 5) BWSEL = 1 (Notes 2, 5) BWSEL = 0 (Note 6) BWSEL = 1 (Note 6) 10% to 90% rise/fall time (Notes 2, 7) Figure 1 (Note 2) 20 log (VDEASSERT/VASSERT), VTH = 6mVP-P (Note 8) VTH = 30mVP-P (Notes 2, 8) 330 < RTH < 2.0k (Notes 2, 8) 330 < RTH < 2.0k (Notes 2, 8) 5 1 2 4 8 -30 10 44 37 10 6.1 3.8 130 63 350 20 8 8 30 +30 100 60 2.5 120 180 1600 30 VCC mVP-P V mV % A 1.7 10 1200 61 44 20 psRMS psP-P ns s dB psP-P s mVP-P 0.77 SYMBOL CONDITIONS MIN TYP 78 1.0625 2.125 0.89 1.0 2.0 GHz MAX 99 UNITS mA Gbps
2
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Dual-Rate Fibre Channel Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.)
PARAMETER Data Output Edge Speed SYMBOL CONDITIONS 20% to 80%, BWSEL = 0 (Notes 2, 5) 20% to 80%, BWSEL = 1 (Notes 2, 5) LOS asserted LOS Current Sink LOS not asserted, VCC = 0, 4.7k pullup to +5.5V LOS not asserted LOS asserted, VCC = 0, 4.7k pullup to +5.5V LOS, LOS sink current = 1mA 10kHz f < 1MHz (Note 9) 1MHz f < 50MHz (Note 9) 40 20 1.0 0 1.0 0 10 0.5 10 MIN TYP 170 105 MAX 220 140 UNITS psP-P mA A mA A V mVP-P
MAX3274/MAX3276
LOS Current Sink LOS, LOS Output Low Voltage Supply Noise Tolerance
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Measured with a -50dBm input signal on a network analyzer. Specifications are guaranteed by design and characterization. Using 27 - 1 PRBS pattern. The input bandwidth is limited to 0.75 (selected data rate) by a 4th-order Bessel Thompson filter. Using a K28.5 pattern at the selected bit rate. Measured differentially into a matched external load. Using a K28.7 or equivalent pattern at the selected bit rate. Measured over the entire input voltage range. Total jitter is estimated as TJ = DJ + 14 x RJ, where DJ is the peak-to-peak deterministic jitter, and RJ is the RMS random jitter. LOS (open collector) is connected to a +5.5V supply through a 4.7k external resistor. Using K28.7 or equivalent pattern at selected bit rate. Total jitter, deterministic jitter, LOS hysteresis, LOS assert performance verified.
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3
Dual-Rate Fibre Channel Limiting Amplifiers MAX3274/MAX3276
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
INPUT = 1.2VP-P, 27 - 1 PRBS, BWSEL = 1
MAX3274/76 toc01
INPUT = 10mVP-P, 27 - 1 PRBS, BWSEL = 1
MAX3274/76 toc02
150mV/div
150mV/div
100ps/div
100ps/div
INPUT = 1.2VP-P, 27 - 1 PRBS, BWSEL = 0
MAX3274/76 toc03
INPUT = 10mVP-P, 27 - 1 PRBS, BWSEL = 0
MAX3274/76 toc04
150mV/div
150mV/div
200ps/div
200ps/div
INPUT RELAXATION OSCILLATION (RO) OF LEGACY FIBRE CHANNEL TRANSMITTERS (INPUT = K28.5, 1.0625Gbps)
MAX3274/76 toc05
BWSEL = 1 RO NOT SUPPRESSED
MAX3274/76 toc06
BWSEL = 0 RO FULLY SUPPRESSED
MAX3274/76 toc07
1mV/div
140mV/div
140mV/div
200ps/div
200ps/div
200ps/div
4
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Dual-Rate Fibre Channel Limiting Amplifiers
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
TRANSFER FUNCTION
MAX3274/76 toc08
MAX3274/MAX3276
SUPPLY CURRENT vs. TEMPERATURE
MAX3274/76 toc9
FORWARD DIFFERENTIAL GAIN (INPUT LEVEL of -60dBm, BWSEL = 0)
44 38 32 GAIN 26 20 14 8 2 -4
MAX3274/76 toc10
1400 DIFFERENTIAL OUTPUT (mVP-P) 1200 1000 800 600 400 200 0 0 5 10 15 20
200 180 160 SUPPLY CURRENT (mA) 140 120 100 80 60 40 20 0
50
25
0
20
40
60
80
100
-10 100M
1G FREQUENCY (Hz)
10G
DIFFERENTIAL INPUT (mVP-P)
TEMPERATURE (C)
INPUT DIFFERENTIAL RETURN GAIN (SIGNAL LEVEL of -60dBm)
MAX3274/76 toc11
OUTPUT DIFFERENTIAL RETURN GAIN (SIGNAL LEVEL of -60dBm)
0 -5 -10 GAIN (dB) -15 -20 -25 -30 -35 -40
MAX3274/76 toc12
ASSERT/DEASSERT LEVELS vs. RTH (BWSEL = 1, 2.125Gbps, K28.5)
MAX3274/76 toc13
0 -5 -10 -15 GAIN (dB) -20 -25 -30 -35 -40 -45 -50 1G FREQUENCY (Hz)
5
70 60 50 DEASSERT 40 30 20 10 ASSERT 0
LOS ASSERT/DEASERT (mVP-P)
10G
1G FREQUENCY (Hz)
10G
0
500
1000
1500 RTH ()
2000
2500
3000
LOS HYSTERESIS vs. TEMPERATURE (BWSEL = 1, 2.125Gbps, K28.5)
MAX3274/76 toc14
DETERMINISTIC JITTER
MAX3274/76 toc15
RANDOM JITTER
MAX3274/76 toc16
10 9 8 HYSTERESIS (dB) 7 6 5 4 3 2 1 0 0 20 40 60 80 RTH = 680 RTH = 1.8k RTH = 330
50 45 DETERMINISTIC JITTER (psP-P) 40 35 30 25 20 15 10 5 0 BWSEL = 1 BWSEL = 0
14 12 RANDOM JITTER (psRMS) 10 8 6 4 2 0 BWSEL = 1 BWSEL = 0
100
0 100 200 300 400 500 600 700 800 900 1000 DIFFERENTIAL INPUT (mVP-P)
0
20 40 60 80 100 120 140 160 180 200 DIFFERENTIAL INPUT (mVP-P)
TEMPERATURE (C)
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5
Dual-Rate Fibre Channel Limiting Amplifiers MAX3274/MAX3276
Pin Description
PIN 1 2 3, 7, 10 4 5 6 8, 13, 16 9 11 12 14 NAME IN+ INVCC BWSEL TEST SQUELCH GND TH OUTOUT+ LOS Noninverted Data Input Inverted Data Input Supply Voltage Bandwidth Select Pin. When BWSEL is set to a TTL-low level or left open, a 4th-order Bessel Thompson filter suppresses relaxation oscillations from legacy CD laser transmitters. Connect BWSEL to a TTL-high for operation above 1.0625Gbps. Test Pin Should Be Connected to Ground Squelch Input. The squelch function is disabled when SQUELCH is set to a TTL-low. When SQUELCH is set to a TTL-high level, and LOS is asserted, the data outputs (OUT+ and OUT-) are forced to static levels. Supply Ground Loss-of-Signal Threshold. A resistor connected from this pin to ground sets the input signal level at which the loss-of-signal (LOS) outputs are asserted. See the Typical Operating Characteristics and Design Procedure sections for more information. Inverted Data Output Noninverted Data Output Inverted Loss-of-Signal Output. LOS is high when the level of the input signal is above the preset threshold set by the TH pin. LOS is asserted low when the input signal level drops below the threshold. Loss-of-Signal Output. LOS is low when the level of the input signal is above the preset threshold set by the TH pin. LOS is asserted high when the input signal level drops below the threshold. Ground. The exposed paddle must be soldered to the circuit board ground for proper thermal and electrical performance. FUNCTION
15 EP
LOS Exposed Pad
6
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Dual-Rate Fibre Channel Limiting Amplifiers
Detailed Description
Figure 2 is a functional diagram of the MAX3274/ MAX3276 limiting amplifiers. Typical gain is 46dB. A linear input drives a bandwidth selector. An offset correction loop with lowpass filtering ensures low deterministic jitter. An integrated RMS signal detector monitors for loss-of-signal conditions. The output buffer provides a limited CML output signal.
VDEASSERT VIN VASSERT LOS RESPONSE TIME LOS, LOS OUTPUTS 50 50
MAX3274/MAX3276
Input Buffer
The MAX3274/MAX3276 input buffer (Figure 3) provides a 100 input impedance between IN+ and IN-. DCcoupling the inputs is not recommended; doing so prevents proper functioning of DC offset correction circuitry.
Figure 1. LOS Response Time
Design Procedure
Programming the LOS Assert Threshold
External resistor R TH programs the loss-of-signal threshold. See the LOS Threshold vs. RTH graph in the Typical Operating Characteristics section. RTH can be estimated by RTH = 15 / VTH, where VTH is the peak-topeak differential input assert level.
Signal Detect and Loss-of-Signal
An RMS signal detector looks at the signal from the input buffer and compares it to a threshold set by a resistor at pin TH. The status of the signal-detect information appears at the LOS outputs. These are opencollector outputs and require external pullup resistors connected to the host power supply. The LOS outputs are high impedance when the power supply to the MAX3274/MAX3276 is 0V. ESD protection on the dualrate limiting amplifiers' LOS outputs do not forward-bias when the power supply of the MAX3274/MAX3276 is 0V or below the host power supply.
Selecting the AC-Coupling Capacitors
The input and output AC-coupling capacitors (C IN , COUT) should be selected to minimize the receiver's deterministic jitter. Lowering the low-frequency cutoff reduces deterministic jitter. The low-frequency cutoff can be determined by:
fC = 1 2 x C x (RL + RS )
Offset Correction
A low-frequency feedback loop is integrated into the limiting amplifiers to reduce input offset and thereby minimize duty-cycle distortion. For proper operation, the input must be externally AC-coupled. The offset correction circuit has been optimized for the Fibre Channel character set, disparity rules, and 8b/10b data encoding. This dictates an average data input mark density of 50% and a maximum run length of five consecutive identical digits (CID) or bits.
where RL is the single-ended load impedance and RS is the single-ended source impedance. CIN, COUT = 0.1F is recommended.
Applications Information
Optical Hysteresis
In an optical receiver, the electrical power change at the limiting amplifier is 2 times the optical power change. For example, if a receiver's optical input power () increases by a factor of 2, and the preamplifier is linear, then the voltage input to the limiting amplifier also increases by a factor of 2. The optical power change is 10log (2/) = 10log(2) = 3dB. At the limiting amplifier, the electrical power change is:
CML Output Buffer
The MAX3274/MAX3276 CML outputs (Figure 4) provide high tolerance to impedance mismatches and inductive connectors. The output current is approximately 24mA for the MAX3274 and 18mA for the MAX3276. The squelch function is enabled when SQUELCH is set to a TTL-high level or connected to VCC. The squelch function holds OUT+ and OUT- at a static voltage when the input signal level drops below the loss-of-signal threshold. The output buffer can be AC- or DC-coupled to the load. For DC operation, the load must be terminated to VCC of the MAX3274/MAX3276.
(2VIN )2 / RIN 10log
VIN2 / RIN
= 10log 22 = 20log (2) = 6dB
()
The typical voltage hysteresis for the MAX3274/ MAX3276 is 6dB. This provides an optical hysteresis of 3dB.
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7
Dual-Rate Fibre Channel Limiting Amplifiers MAX3274/MAX3276
OFFSET CORRECTION LPF
4TH-ORDER LP FILTER IN+ INBWSEL TH SQUELCH
0 1
OUT+ OUT-
RMS SIGNAL DETECT
LOS
LOS
Figure 2. Functional Diagram of the MAX3274/MAX3276 Limiting Amplifier
VCC
VCC
50 IN+
50
50/75
50/75 OUT+ OUT-
INDATA ESD STRUCTURES ESD STRUCTURES
Figure 3. Input Circuit
Figure 4. CML Output Circuit
8
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Dual-Rate Fibre Channel Limiting Amplifiers MAX3274/MAX3276
Pin Configuration
GND GND LOS LOS TOP VIEW
Chip Information
DEVICE COUNT: 2855 TRANSISTOR COUNT: 1310 PROCESS: BiPOLAR: SiGe, SOI
16
15
14
13
IN+
1
12
OUT+
IN-
2
MAX3274 MAX3276
11
OUT-
VCC BWSEL
3
10
VCC TH
4 EXPOSED PAD
9
5
6
7
VCC
TEST
TOP VIEW 16-PIN QFN (4mm x 4mm)
_______________________________________________________________________________________
SQUELCH
GND
8
9
Dual-Rate Fibre Channel Limiting Amplifiers MAX3274/MAX3276
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12,16,20, 24L QFN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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